1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method to form a contactless array for high density nonvolatile memories.
2. Description of the Related Art
Traditionally, advances in the reduction of EPROM memories have concentrated on pushing the limits of optical lithography and plasma etching. The cell frequently used by the industry is the cell shown in FIG. 1. This cell uses locally oxidized silicon (LOCOS) to isolate individual bits. A half contact per cell is required to connect drain diffusions to the metal bit lines. Though the source/drain diffusions 100 are self-aligned to the polysilicon floating gates 102, optical registration is required to align the floating gate 102, word lines 104 and contacts to the field oxide.
A. T. Mitchell et.al. proposed a process which is used to construct a Floating gate Avalanche injection MOS (FAMOS) device which does not require the use of LOCOS isolation on contacts in the array. The cell is filly self-aligned and therefore does not place any alignment restrictions on conventional optical lithography. The cell is called SPEAR for Self-aligned Planar EPROM Array. Process steps for the fabrication of SPEAR FAMOS are depicted through FIG. 2A to 2D. Two adjacent transistors are shown in these pictures to indicate how the process would be used in an array formation. Referring to FIG. 2A, samples are fabricated on, for example, 12 ohm-cm &lt;100&gt; silicon substrates 200. Conventional LOCOS isolation is used to isolate peripheral devices, but is not used in the formation of the SPEAR cell. After field isolation, an array implant is performed through a dummy oxide to set the FAMOS threshold voltage. The FAMOS gate oxide 202, having a thickness of about 350 .ANG., is then grown. A polysilicon layer 204 is then deposited and defined, using a patterned photoresist layer 206 as a mask, to form long continuous polysilicon slots 205. The width of the polysilicon slots 205 also defines the length of the FAMOS transistor. Next, arsenic is implanted in the polysilicon slots 205 forming the buried N.sup.+ bit lines 208 and also acting as the source and drain for the FAMOS transistor. Referring then to FIG. 2B, a conformal CVD TEOS (tetraethyl orthosilicate) oxide 210 is deposited to fill in the slots 205 and a planarizing photoresist 212 is spun on the wafer. A second resist coat and pattern, applied after the planarization resist coating, was then used to protect the periphery region by opening only the array area. As shown in FIG. 2C, a planarizing plasma etch that etches both the oxide layer 210 and the photoresist layers 212 at the same rate is used to remove the TEOS oxide 210 over the polysilicon slots 205, thus exposing the surface of the polysilicon layer 204 yet leaving oxide in the slots 205 over the buried bit lines 208. The planarization process is called oxide Resist-Etch-Back (REB). Referring to FIG. 2D, interlevel dielectric layer 214 with an effective oxide thickness of 350 .ANG. (consisting of interlevel oxide and interlevel nitride) and a polysilicon layer 216 are then deposited. The polysilicon layer 216, interpoly dielectric layer 214 and polysilicon layer 204 are all etched to complete the formation of the polysilicon floating gate and to form the polysilicon word lines.
top view of the conventional cross-point EPROM cell proposed by A. T. Mitchell et.al. is shown in FIG. 3, drawn with a proposed 1 .mu.m design rule, wherein the reference number 301, 302 and 303 represent the word line 301, bit line 302 and floating gate 303, respectively. Comparing the SPEAR cell proposed by A. T. Mitchell with the industry standard cell shown in FIG. 1, it is found that the SPEAR cell is less than half the size of the industry standard cell.
However, during the process of manufacturing such a SPEAR cell the REB process used to planarize the interlevel oxide between poly 1 lines in the array which creates plasma-induced damage and plasma-process-induced particle contamination. Plasma consists of energized ions, electrons, and excited molecules. When the excited particles recombine, they give off photons having an energy of a few eV. In addition, ion and electron bombardment may all contribute to damage mechanisms. Plasma-induced damage can take many forms, such as a trapped interface charge, and material defects migration into bulk materials. Moreover, plasma processes can generate a large number of particles on the wafer surface during etching. These particles range in size from less than a quarter of a micrometer to tens of micrometers at a density of over 10.sup.7 cm.sup.-3, and they can fall on the wafer surface when the plasma in turned off